An IP block called the “Generic Interrupt Controller” (GIC) receives all the interrupt signals, processes them, and drives the IRQ signal if certain conditions are met. On the ZYNQ device, nearly 100 interrupt signals are generated by the IP blocks and FPGA that surround the ARM processor, but there is only one IRQ input signal. That vector typically jumps to an interrupt handler subprogram to determine the cause of the interrupt, and to branch to code to deal with the specific interrupt. Immediately after the IRQ signal is asserted, the next instruction to be executed will be loaded from the IRQ vector stored in the vector table. This discussion focuses on the standard IRQ system. They are very similar, except the FIQ minimizes the time taken for context switching. The ARM processor has two interrupt input signals called IRQ (interrupt request) and FIQ (fast interrupt request). Internally generated faults are discussed separately. This document discusses the ARMs response to external interrupts. You can read more about operating modes and exceptions here: Exceptions Processor Modes Switching to privileged mode stores copies of the stack pointer (SP), link register (LR), and CPSR in dedicated “shadow registers”, and allows certain privileged actions (like modifying the CSPR).
When one of the seven exceptions occur, the corresponding vector is automatically loaded into the PC, and the ARM automatically switches out of User mode and into a corresponding “privileged” operating mode. Each exception type has its own vector, and the vectors are stored in a section of consecutive memory locations called a vector table. They include a system reset, an attempt to execute an undefined instruction, an aborted instruction fetch, an aborted data memory cycle, an aborted hypervisor call, and IRQ and FIQ interrupt signal assertions. ZYNQ’s ARM processor defines seven types of exceptions. The exception handler preserves context (i.e., makes copies of all CPU registers), deals with the event that caused the exception, restores context, and then returns to the normal program flow. That address is called the “exception vector”, and the instruction stored there is typically a jump to an user-written “exception handler” subroutine. When an exception occurs, the processor interrupts normal program execution, and fetches its next instruction from a specially designated address that corresponds to the type of exception. ARM program execution is automatically interrupted when certain exceptions occur, like the assertion of an externally generated interrupt, or the occurrence of an internal fault like an attempt to execute an undefined instruction.
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